1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory cell matrix providing divided write/erase for high-density memory cell transistors having a floating gate or MONOS structure, a method for operating thereof, and a monolithic integrated circuit and a nonvolatile semiconductor memory system.
2. Description of the Related Art
In the related art, for example, an EEPROM (Electrically Erasable Programmable Read-Only Memory), which electrically writes and erases data, is known as a nonvolatile semiconductor memory, as described in Riichiro Shirota, “A Review of 256 Mbit NAND Flash Memories and NAND Flash Future Trend”, Non-Volatile Semiconductor Memory Workshop (NVSMW), 2000, pp. 22-31.
An EEPROM, especially in the case of a NAND, has memory cell transistors at respective intersections of word lines in a row direction and bit lines in a column direction arranged to form a memory cell array. As the memory cell transistor, such as a MOS transistor having a stacked-gate structure where a floating gate and a control gate are overlaid is generally used.
A typical memory cell of the NAND flash memory is disclosed in Riichiro Shirota, “A Review of 256 Mbit NAND Flash Memories and NAND Flash Future Trend”, Non-Volatile Semiconductor Memory Workshop (NVSMW), 2000, pp. 22-31. The NAND flash memory has a structure where a plurality of memory cell transistors connected in series to form a NAND string, on both sides of which select gate transistors are arranged. Furthermore, an element isolation region is disposed parallel to the element active area region of the memory cell transistor to form a memory cell array. Generally, the gate length of the select gate transistors is the same or longer than the gate length of the memory cell transistors to prevent degradation of cutoff characteristics of the transistors due to a short-channel effect. Moreover, the select gate transistor is usually constituted by an enhancement mode MOS transistor.
The high-density of the memory cell transistors of the NAND flash memory is realized by increasing the number of NAND columns. In other words, while the select gate transistors, and the bit-line and/or source-line contact portions are an overhead of the memory cell array, in order to decrease the rate at which the select gate transistors occupy, a higher density is achieved by increasing the number of memory cell transistors contained in a NAND column and thus decreases the rate of the overhead. However, if the number of memory cell transistors contained in a NAND column increases, a problem occurs that a unit of data in writing/erasing also becomes larger because data is rewritten for each NAND column. Hence, a method where the NAND column is divided by providing the select gate transistor in the memory cell string, and the like have been proposed in Japanese Laid-Open Patent Application No. 2000-222895 and U.S. Pat. No. 6,295,227. In addition, a self-boost (SB) write method and the like have been proposed by K. D. Suh, et al., “A 3.3V 32 Mb NAND Flash Memory with Incremental Step Pulse Programming Scheme”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol. 30, No. 11, November 1995, pp. 1149-1156, as a method of controlling a channel-voltage when writing.
With the method where NAND columns are divided, while the increase of the overhead associated with the bit line and source line previously mentioned can be avoided, the region of the high-density memory cell inevitably increases because the overhead region of the select gate transistor itself increases. In addition, since positions of the select gate transistors are fixed from the stage of designing the memory, the degree of freedom in changing the unit in writing/erasing when using the memory is small.